Thumbnailing happens in a background process and shouldn’t block the main thread; rather hangs are usually because fetching xattr over SMB is slow and Finder will block until it’s enumerated the metadata of every file in a folder.
Preview actually does use progressive rendering for large enough images, even from SSDs. You can tell because opening an image will be blurry for several seconds, even when the full size image could have been decoded in a quarter second or less.
You're wrong. AVIF does support spatial layering where the full-resolution image is derived from the lower-resolution layer, and cannot be decoded independently.
Yes, the format is not inherently progressive. But having the fine steps in progressive quality that JPEG-2000 and JPEG-XL have has less general usefulness than the amount of words complaining about it.
For like a decade, the "opt-in" to ACR was included in the ToS agreement needed to use any smart features. Then at least some brands made the opt-in separate, but made it look like a recommendation engine or "help us improve your experience" agreement.
LG adopted the "Maybe Later" dark pattern for opt-in to ACR, at least in some markets. Though I guess you never know for sure with A/B testing.
We really need a GDPR-like law that makes it clear that goading users into accepting ToS like this cannot constitute a contract and instead invalidates the agreement for everyone.
The C1-ultra has a decode of 10 instructions but can issue up to 23 uop per cycle, that’s a good bit wider than any other CPU. In particular, I believe it’s the first CPU to have a 4th load pipeline.
All 10 cores support the same extensions. It’s silly to implement an SoC any other way, and it’s been a decade since someone has last made that mistake.
It's been a long time since anyone tried to actually ship a chip with different instruction set support enabled across its cores, but Intel has spent the past several years shipping consumer parts where they had to disable some features (AVX-512) on their P-cores to bring them down to the level of what their E-cores support, because they didn't plan ahead for doing a heterogeneous chip with those two microarchitectures. Toggling off some instructions in microcode for some cores is quite different from having two microarchitectures that are each designed to implement the same instruction set but with different performance and power characteristics.
Well the original article is also about RISC-V isn't a great ISA for embedded either, and how that's supremely disappointing because there's no inherent reason why the designers couldn't have learned from decades of ISA research and made it suck even a little less. OP doesn't even defend the ISA committee (unlike HN, somehow...)
As much as people complain about warts in other ISAs like x86, their design decisions made sense back when they were made (or at least, no one really knew better)
There's an order of magnitude difference in speed requirements between file format parsing and image decoding, then another order of magnitude difference to video decoding. Even rav1d reuses dav1d's assembly (most of the actual runtime) to approach its speed.
Preview actually does use progressive rendering for large enough images, even from SSDs. You can tell because opening an image will be blurry for several seconds, even when the full size image could have been decoded in a quarter second or less.
reply